(1) Field of the Invention
The present invention relates to a multiphase converting controller, and more particularly relates to a multiphase converting controller that adjusts a length of the conduction time period according to a mode signal.
(2) Description of the Prior Art
FIG. 1 is a schematic diagram of a conventional multiphase converting controller. Herein, take two phases (converting circuits) for example. Converting circuits 2 and 4 are coupled to an input voltage Vin and separately comprises high-side transistors MU1 and MU2, low-side transistors ML1 and ML2 and inductances L1 and L2. Output ends of the converting circuits 2 and 4 are coupled to an output capacitance C to commonly supply an output voltage Vout. A multiphase converting controller 10 controls the converting circuits 2 and 4 in sequence. The system provides a mode signal Sm for notice when entering into a light load state, and the multiphase converting controller 10 executes the phase reducing operation when receiving the mode signal Sm. The conventional controller always keeps the first phase work and sheds the second phase, i.e., the converting circuit 2 continues operating and the converting circuit 4 stops operating. Thus, it can reduce the switch loss to raise the efficiency in light load.
The conventional controller always keeps certain phase (such as the first phase) operate. It causes the workloads of the power transistors and the inductances of the phases to unbalance. The certain phase will damage earlier than other phases, and so the life-span of the whole circuit is shortened.
FIG. 2 is a schematic diagram of a control circuit of a power supply circuit disclosed in the TW patent publication No. 201034356 applied by RICHTEK Technology Corporation. An error amplifier EA compares a feedback signal FB with an output voltage reference signal Vref and then generates an error amplification signal. The error amplification signal is inputted to pulse width modulating comparators PWM1 and PWM2 corresponding to different phases. Operation amplifiers OP1 and OP2 compare voltage signals ISEN1, ISEN1_N, ISEN2 and ISEN2_N at two ends of phase current detecting resistors, and accordingly measure phase currents and generate corresponding current amplification signals. The current amplification signals are input into corresponding pulse width modulating comparators PWM1 and PWM2. The gate control circuit 14 generates driving signals UG1, LG1, UG2 and LG2 to drive the corresponding power transistors.
An external phase control signal PSC determines whether executing the phase reducing operation. When a phase selecting circuit 16 receives the external phase control signal PSC, the control circuit is triggered to determine whether entering to the phase reducing operation. When determining that the phase reducing operation is necessary, the control circuit controls the gate control circuit 14 to turn off one or more phases. The pause phase(s) is not fixed during the phase reducing operation.
The Richtek uses the phase selecting control to change the pause phase with different phase reducing operations for balancing the workload of the phases. Actually, every time the circuit is restarted, the control circuit will execute the phase reduction operation to pause phase from a default first phase. Therefore, the workloads of the power transistors and the inductances among the phases are still obviously unbalanced.
In other words, to execute the phase reducing in the prior art can not balance the workloads of the power transistors and the inductances. Consequently, the phase having the heavier workload will damage earlier than other phases having the lighter workload, and so the life-span of the whole circuit is shortened.